1. Field of the Invention
Embodiments of the invention relate generally to a semiconductor memory devices. More particularly, embodiments of the invention relate to a semiconductor memory device adapted for use with a word line addressing method capable of reducing coupling noise between neighboring word lines during a continuous read operation.
This application claims priority to Korean Patent Application No. 10-2006-52 filed Jan. 2, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
In semiconductor memory devices such as synchronous flash memory, continuous read operations are commonly performed. A “continuous read operation” allows a plurality of word lines to be continuously and sequentially selected in a synchronous manner using one or more reference clock signals to read data. During a continuous read operation, one word line in the plurality of word lines, as selected during one clock cycle, is deactivated at about the same time as a next word line is activated during a next clock cycle.
FIG. 1 is a partial circuit diagram illustrating a conventional word line addressing method. The diagram illustrates part of a memory array 10 for a NOR-type nonvolatile semiconductor memory device. Referring to FIG. 1, a plurality of memory cells (MCs) are arranged in a matrix at the intersections of word lines 11 to 18 and bit lines BL<1:512>. As is customary, word lines 11 to 18 are arranged parallel.
In the conventional semiconductor memory device of FIG. 1, word lines 11 to 18 are sequentially addressed (i.e., selected) in an “upward” manner, (e.g., a sequence of WL<1>, WL<2>, WL<3>, WL<4>, etc.). Within the context of this addressing scheme, which is often used in conventional continuous read operations, coupling noise is generated on neighboring (e.g., physically adjacent of closely proximate) word lines as word lines 11 to 18 are continuously selected by the addressing sequence.
Referring to FIG. 2, during a first selection interval P1, a first word line 11, (WL<1>) having a first address is selected and activated at time t1. This event is immediately following by a second selection interval P2 in which a second word line 12, (WL<2>) having a second address is selected and activated. During the second selection interval P2, previously activated first word line 11 (WL<1>) is deactivated at time t2. Simultaneously (or nearly simultaneously), second word line 12 (WL<2>) is activated at time t3. This coincidental deactivation/activation of neighboring word lines causes noise to be coupled onto the word line being activated. See, for example, portion A of FIG. 2. This noise is generated, for example, as first word line 11 (WL<1>) is switched from a read voltage (VREAD) signal to a ground voltage (VSS), and the second word line 12 (WL<2>) is switched from the ground voltage (VSS) to the read voltage (VREAD). The coupling noise thus generated may actually delay the activated of second word line 12 (WL<2>) in particularly bad instances.
Thus, the continuous read operation, as executed in conventional semiconductor memory devices, may be characterized by the problem delayed word line activation due to noise coupled from neighboring word lines. This problem becomes more serious as the physical separation between neighboring word line decreases due to increased device density and as activation intervals decrease as operating frequency increases.